This section introduces aspects that may help facilitate a better understanding of the invention. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.
There are many applications in which data is transmitted between two different sets of circuitry operating at the same clock speed, but with unknown, and possibly varying, phase offset between those two clock domains. Depending on the particular situation, the two different sets of circuitry may reside on two different integrated circuits (i.e., chips) or on the same chip that is segmented into the two (or more) different clock domains. Note that, in some applications, the two clock domains also correspond to different power domains.
When data is transmitted from a first clock domain (referred to herein as Domain A) to a second clock domain (referred to herein as Domain B), the Domain A circuitry is said to have transmit (TX) circuitry designed to generate and transmit the outgoing data and the Domain B circuitry is said to have receive (RX) circuitry designed to receive and process the incoming data. Note that, for applications in which data is also transmitted from Domain B to Domain A, the Domain B circuitry will also be configured with an instance of the TX circuitry, and the Domain A circuitry will also be configured with an instance of the RX circuitry.
In order for the RX circuitry operating under the Domain B clock (CLKB) to be able to handle the received data transmitted from the TX circuitry operating under the Domain A clock (CLKA), the RX circuitry is implemented with phase-alignment circuitry that accommodates the phase offset between the TX clock signal CLKA of the TX circuitry and the RX clock signal CLKB of the RX circuitry.
One conventional solution is to transmit a copy of the TX clock signal CLKA from the TX circuitry to the RX circuitry, which is configured with a phase-locked loop (PLL) circuit that forces the phase of the RX clock signal CLKB to be substantially aligned with the phase of the received TX clock signal CLKA. Such PLL-based TX clock data recovery (TXCDR) solutions are disadvantageous to implement due to the size, complexity, and power consumption of the PLL circuit. In addition, TXCDR solutions do not deliver the desired system stability when a low-speed jittery clock is used to modify high-frequency macro PLL clock outputs.
Another conventional solution is to provide synchronous FIFO (first-in, first-out) buffers in the RX circuitry, where the data is received into the FIFO buffers under the TX clock domain, but read out from the FIFO buffers under the RX clock domain. Although this solution is satisfactory for many applications, it is not acceptable for certain low-latency applications due to the one- to two-cycle delay added by the FIFO buffers.